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74LVT162374DL Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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74LVT162374DL Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 12 page 9397 750 14401 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 17 January 2005 9 of 17 Philips Semiconductors 74LVT162374 3.3 V 16-bit edge-triggered D-type flip-flop [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C. [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C. tPHL propagation delay nCP to nQn see Figure 6 VCC = 3.3 V ± 0.3 V 1.5 3.0 4.9 ns VCC = 2.7 V - - 5.1 ns tPZH output enable time to HIGH-level see Figure 7 VCC = 3.3 V ± 0.3 V 1.5 3.5 5.6 ns VCC = 2.7 V - - 6.9 ns tPZL output enable time to LOW-level see Figure 8 VCC = 3.3 V ± 0.3 V 1.5 3.2 4.9 ns VCC = 2.7 V - - 6.0 ns tPHZ output disable time from HIGH-level see Figure 7 VCC = 3.3 V ± 0.3 V 1.5 3.5 5.4 ns VCC = 2.7 V - - 5.7 ns tPLZ output disable time from LOW-level see Figure 8 VCC = 3.3 V ± 0.3 V 1.5 3.2 5.0 ns VCC = 2.7 V - - 5.1 ns Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 10. Symbol Parameter Conditions Min Typ Max Unit Table 9: Dynamic characteristics set-up requirements GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +85 °C [1] tsu(H), tsu(L) set-up time nDn to nCP see Figure 9 VCC = 3.3 V ± 0.3 V 2.0 0.7 - ns VCC = 2.7 V 2.0 - - ns th(H), th(L) hold time nDn to nCP see Figure 9 VCC = 3.3 V ± 0.3 V 0.8 0 - ns VCC = 2.7 V 0.1 - - ns tW(H) nCP pulse width HIGH see Figure 6 VCC = 3.3 V ± 0.3 V 1.5 0.6 - ns VCC = 2.7 V 1.5 - - ns tW(L) nCP pulse width LOW see Figure 6 VCC = 3.3 V ± 0.3 V 3.0 1.6 - ns VCC = 2.7 V 3.0 - - ns |
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