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74LVCH32373A Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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74LVCH32373A Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 1999 Nov 24 3 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. ORDERING INFORMATION PINNING OPERATING MODE INPUTS INTERNAL LATCHES OUTPUTS nOE nLE nDn nQn Enable and read register (transparent mode) L H LLL L HHHH Latch and read register L L l L L LLh H H Latch register and disable outputs HL l L Z HL hH Z TYPE NUMBER PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVCH32373AEC −40 to +85 °C 96 LFBGA96 plastic SOT536-1 SYMBOL DESCRIPTION nDn data inputs nLE latch enable inputs (active HIGH) nQn data outputs GND ground (0 V) nOE output enable inputs (active LOW) VCC DC supply voltage |
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