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74LV4060PWDH Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74LV4060PWDH Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 18 page Philips Semiconductors Product specification 74LV4060 14-stage binary ripple counter with oscillator 2 1998 Jun 23 853-2076 19619 FEATURES • Wide operating voltage: 1.0 to 5.5 V • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between V CC = 2.7 V and VCC = 3.6 V • Typical V OLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C. • Typical V OHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25 °C. • All active components on chip • RC or crystal oscillator configuration • Output capability: standard (except for R TC and CTC) • I CC category: MSI APPLICATIONS • Control Counters • Timers • Frequency Dividers • Time-delay circuits DESCRIPTION The 74LV4060 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT4060. The 74LV4060 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC) floating. The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of the other input conditions. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf < 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay CL = 15 pF RS to Q3 VCC = 3.3 V 29 tPHL/tPLH Qn to Qn+1 6 ns tPHL MR to Qn 16 f Maximum clock frequency 99 MHz fmax Maximum clock frequency 99 MHz C1 Input capacitance 3.5 pF C Power dissipation capacitance per package Notes 1, 2 and 3 40 pF CPD Power dissipation capacitance per package 40 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW) PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of the outputs. 2. The condition is V1 = GND to VCC 3. For formula on dynamic power dissipation, see the following pages. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40 °C to +125°C 74LV4060 N 74LV4060 N SOT38-4 16-Pin Plastic SO –40 °C to +125°C 74LV4060 D 74LV4060 D SOT109-1 16-Pin Plastic SSOP Type II –40 °C to +125°C 74LV4060 DB 74LV4060 DB SOT338-1 16-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV4060 PW 74LV4060PW DH SOT403-1 |
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