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74LV4066N Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74LV4066N Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74LV4066 Quad bilateral switches 2 1998 Jun 23 853-2077 19619 FEATURES • Optimized for Low Voltage applications: 1.0V to 6.0V • Accepts TTL input levels between V CC = 2.7 V and VCC = 3.6 V • Typical V OLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C. • Very low typ “ON” resistance: 25 W at VCC – VEE = 4.5 V 35 W at VCC – VEE = 3.0 V 60 W at VCC – VEE = 2.0 V • Output capability: non-standard • I CC category: SSI DESCRIPTION The 74LV4066 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT4066. The 74LV4066 has four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH enable input (nE). When nE is LOW the corresponding analog switch is turned off. The 74LV4066 has an on resistance which is dramatically reduced in comparison with 74HCT4066. FUNCTION TABLE INPUTS SWITCH nE SWITCH L off H on NOTES: H = HIGH voltage level L = LOW voltage level QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf v 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPZH/tPZL Turn “ON” time: nE to VOS CL = 15pF RL =1KW 10 ns tPHZ/tPLZ Turn “OFF” time: nE to VOS RL = 1KW VCC= 3.3V 13 ns CI Input capacitance 3.5 pF CPD Power dissipation capacitance per switch Notes 1, 2 11 pF CS Maximum switch capacitances 8 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; Cs = maximum switch capacitance in pF; {(CL + CS) × VCC2 × Fo} = sum of the outputs. VCC = supply voltage in V. 2. The condition is VI = GND to VCC. ORDERING AND PACKAGE INFORMATION TYPE NUMBER PACKAGES TYPE NUMBER PINS PACKAGE MATERIAL CODE 74LV4066N 16 DIL Plastic SOT27-1 74LV4066D 16 SO Plastic SOT108-1 74LV4066DB 16 SSOP Plastic SOT337-1 74LV4066PW 16 TSSOP Plastic SOT402-1 PIN CONFIGURATION SV01669 12 11 10 9 8 7 6 5 4 3 2 1 13 14 GND VCC 1Y 1Z 2Z 2Y 2E 3E 1E 4E 4Y 4Z 3Z 3Y PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1, 4, 8, 11 1Y – 4Y Independent inputs/outputs 2, 3, 9, 10 1Z – 4Z Independent inputs/outputs 13, 5, 6, 12 1E to 4E Enable input (active HIGH) 7 GND Ground (0V) 14 VCC Positive supply voltage |
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