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74LV257PWDH Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74LV257PWDH Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74LV257 Quad 2-input multiplexer (3-State) 2 1998 May 20 853-1985 19420 FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between V CC = 2.7 V and VCC = 3.6 V • Typical V OLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C • Typical V OHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Non-inverting data path • Output capability: bus driver • I CC category: MSI DESCRIPTION The 74LV257 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT257. The 74LV257 is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1l0 to 4l0) are selected when input S is LOW and the data inputs from source 1 (1l1 to 4l1) are selected when S in HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) from the selected inputs. The 74LV257 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH. The logic equations for the outputs are: 1Y = OE × (1l1 × S + 1l0 × S) 2Y = OE × (2l1 × S + 2l0 × S) 3Y = OE × (3l1 × S + 3l0 × S) 4Y = OE × (4l1 × S + 4l0 × S) QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nl0, nl1 to nY S to nY CL = 15 pF; VCC = 3.3 V 10 14 ns CI Input capacitance 3.5 pF CPD Power dissipation capacitance per gate VI = GND to VCC1 30 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40 °C to +125°C 74LV257 N 74LV257 N SOT38-4 16-Pin Plastic SO –40 °C to +125°C 74LV257 D 74LV257 D SOT109-1 16-Pin Plastic SSOP Type II –40 °C to +125°C 74LV257 DB 74LV257 DB SOT338-1 16-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV257 PW 74LV257PW DH SOT403-1 PIN CONFIGURATION SV00636 1 2 3 4 5 6 S 1I0 1I1 IY 2l0 2l1 VCC OE 4l0 16 15 14 13 12 11 7 8 GND 3l1 3Y 10 9 2Y 4l1 4Y 3l0 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 S Common data select input 2, 5, 11, 14 1l0 to 4l0 Data inputs from source 0 3, 6, 10, 13 1l1 to 4l1 Data inputs from source 1 4, 7, 9, 12 1Y to 4Y 3-state multiplexer outputs 8 GND Ground (0 V) 15 OE 3-State output enable input (active LOW) 16 VCC Positive supply voltage |
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