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74LV240D Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74LV240D Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74LV240 Octal buffer/line driver; inverting (3-State) 2 1998 May 20 853–1923 19422 FEATURES • Wide operating voltage: 1.0 to 5.5 V • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between V CC = 2.7 V and VCC = 3.6 V • Typical V OLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C • Typical V OHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Output capability: bus driver • I CC category: MSI DESCRIPTION The 74LV240 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT240. The 74LV240 is an octal inverting buffer/line driver with 3-State outputs. The 3-State outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74LV240 is identical to the 74LV244 but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay 1An to 1Yn; 2An to 2Yn CL = 15 pF; VCC = 3.3 V 9.0 ns CI Input capacitance 3.5 pF CPD Power dissipation capacitance per buffer VCC = 3.3 V VI = GND to VCC1 30 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 fi ) (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL –40 °C to +125°C 74LV240 N 74LV240 N SOT146-1 20-Pin Plastic SO –40 °C to +125°C 74LV240 D 74LV240 D SOT163-1 20-Pin Plastic SSOP Type II –40 °C to +125°C 74LV240 DB 74LV240 DB SOT339-1 20-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV240 PW 74LV240PW DH SOT360-1 PIN CONFIGURATION SV00607 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1OE 1A0 2Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3 GND 2A3 1Y3 2A2 1Y2 2A1 1Y1 2A0 1Y0 2OE VCC LOGIC SYMBOL SV00608 1A 0 2A 0 2 17 1A 1 2A 1 4 15 1A 2 2A 2 6 13 1A 3 2A 3 8 11 1OE 2OE 1 19 1Y 0 2Y 0 18 3 1Y 1 2Y 1 16 5 1Y 2 2Y 2 14 7 1Y 3 2Y 3 12 9 |
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