1999 Oct 01

2

Philips Semiconductors

Product specification

Octal D-type flip-flop with reset; positive

edge-trigger; open drain outputs

74HCT7273

FEATURES

• ESD protection:

HBM EIA/JESD22-A114-A

Exceeds 2000 V

MM EIA/JESD22-A115-A

Exceeds 200 V

• Ideal buffer for MOS

microprocessor or memory

• Eight positive edge-triggered

D-type flip-flops

• Common clock and master reset

• Output capability: standard (open

drain)

DESCRIPTION

The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible

with Low power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard no 7A.

The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D

inputs and Q outputs. The common Clock (CP) and Master Reset (MR) inputs

load and reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock

A LOW level on the MR input forces all outputs LOW, independently of the clock

or data inputs.

The device is useful for applications requiring true outputs only and clock and

master reset inputs that are common to all storage elements.

The 74HCT7273 has open-drain N-outputs, which are clamped by a diode

the high-impedance OFF-state. The output may now be pulled to any voltage

or HIGH-to-LOW level shifter. For digital operation and OR-tied output

applications, the device must have a pull-up resistor to establish a logic HIGH

level.

QUICK REFERENCE DATA

Notes

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

propagation delay

16

ns

23

ns

maximum clock frequency

56

MHz

input capacitance

3.5

pF

power dissipation capacitance

37

pF