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74HCT7404 Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74HCT7404 Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 28 page September 1993 2 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word and bit dimensions • Pinning arranged for easy board layout: input pins directly opposite output pins • Output capability: driver (8 mA) • ICC category: LSI. APPLICATIONS • High-speed disc or tape controller • Communications buffer. GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Note 1. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC −1.5 V. ORDERING INFORMATION SYMBOL PARAMETER CONDITIONS TYP. UNIT HC HCT tPHL/tPLH propagation delay SO, SI to DIR and DOR CL = 15 pF; VCC = 5 V 15 17 ns fmax maximum clock frequency 30 30 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package note 1 475 490 pF EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE 74HC/HCT7404N 18 DIL plastic SOT102 74HC/HCT7404D 20 SO20 plastic SOT163A |
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