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74HCT7030 Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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74HCT7030 Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 22 page December 1990 9 Philips Semiconductors Product specification 9-bit x 64-word FIFO register; 3-state 74HC/HCT7030 tW SO pulse width HIGH or LOW 100 20 17 33 12 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.9 tW DIR pulse width HIGH 10 5 4 47 17 14 145 29 25 8 4 3 180 36 31 8 4 3 220 44 38 ns 2.0 4.5 6.0 Fig.7 tW DOR pulse width HIGH 10 5 4 47 17 14 145 29 25 8 4 3 180 36 31 8 4 3 220 44 38 ns 2.0 4.5 6.0 Fig.10 tW MR pulse width LOW 70 14 12 22 8 6 90 18 15 105 21 18 ns 2.0 4.5 6.0 Fig.8 trem removal time MR to SI 80 16 14 24 8 7 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.15 tsu set-up time Dn to SI −35 −7 −6 −36 −13 −10 −45 −9 −8 −55 −11 −9 ns 2.0 4.5 6.0 Fig.13 th hold time Dn to SI 135 27 23 44 16 13 170 34 29 205 41 35 ns 2.0 4.5 6.0 Fig.13 fmax maximum clock pulse frequency SI, SO burst mode 9.9 30 36 2.8 14 16 2.4 12 14 MHz 2.0 4.5 6.0 Figs 11 and 12 fmax maximum clock pulse frequency SI, SO using flags 9.9 30 36 2.8 14 16 2.4 12 14 MHz 2.0 4.5 6.0 Figs 6 and 9 fmax maximum clock pulse frequency SI, SO cascaded 7.6 23 27 2.2 11 13 1.8 9.2 11 MHz 2.0 4.5 6.0 Figs 6 and 9 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. |
Codice articolo simile - 74HCT7030 |
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Descrizione simile - 74HCT7030 |
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