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74HCT670D Scheda tecnica(PDF) 5 Page - NXP Semiconductors |
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74HCT670D Scheda tecnica(HTML) 5 Page - NXP Semiconductors |
5 / 9 page December 1990 5 Philips Semiconductors Product specification 4 x 4 register file; 3-state 74HC/HCT670 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf = 6 ns; CL =50pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 −40 to +85 −40 to+125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay RA, RB to Qn 58 21 17 195 39 33 245 49 42 295 59 50 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay WE to Qn 77 28 22 250 50 43 315 63 54 375 75 64 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay Dn to Qn 74 27 22 250 50 43 315 63 54 375 75 64 ns 2.0 4.5 6.0 Fig.7 tPZH/ tPZL 3-state output enable time RE to Qn 39 14 11 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.9 tPHZ/ tPLZ 3-state output disable time RE to Qn 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.9 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 tW write enable pulse width LOW 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.8 tsu set-up time Dn to WE 60 12 10 3 1 1 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.8 tsu set-up time WA, WB to WE 60 12 10 6 2 2 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.8 th hold time Dn to WE 5 5 5 0 0 0 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.8 th hold time WA, WB to WE 5 5 5 0 0 0 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.8 tlatch latch time WE to RA, RB 100 20 17 28 10 8 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.8 |
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