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74HC4510D Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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74HC4510D Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 12 page December 1990 10 Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 Fig.9 Waveforms showing the preset enable pulse width, preset enable to output delays and output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the master reset pulse, master reset to terminal count and Qn delay and master reset to clock removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the data set-up and hold times to parallel load (PL). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
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