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74HCT4059D Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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74HCT4059D Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 20 page 1998 Jul 08 3 Philips Semiconductors Product specification Programmable divide-by-n counter 74HC/HCT4059 If n = 8 479 and the selected mode = 10, the preset value = 8 479/10 with a remainder of 9, thus the JAM inputs must be set as shown in Table 3. To verify: n = 10 (1 000 × 0 + 100 × 8 + 10 × 4 + 1 × 7) + 9 n = 8 479. The three decades of the intermediate counting section can be preset to a binary 15 instead of a BCD 9. In this case the first cycle of a counter consists of 15 count pulses, the next cycles consisting of 10 counting pulses. Thus the place value of the three decades are still 1, 10 and 100. For example, in the divide-by-8 mode, the number from which the intermediate counting section begins to count-down can be preset to: 3rd decade: 1 500 2nd decade: 150 1st decade: 15 The last counting section can be preset to a maximum of 1, with a place value of 1 000. The first counting section can be preset to a maximum of 7. To calculate n: n = 8 (1 000 × 1 + 100 × 15 + 10 × 15 + 1 × 15) + 7 n = 21 327. 21 327 is the maximum possible count in the divide-by-8 mode. The highest count of the various modes is shown in the Function table, in the column entitled “binary counter range”. The mode select inputs permit, when used with decimal programming, a non-BCD least significant digit. For example, the channel spacing in a radio is 12.5 kHz, it may be convenient to program the counter in decimal steps of 100 kHz subdivided into 8 steps of 12.5 kHz controlled by the least significant digit. Also frequency synthesizer channel separations of 10, 12.5, 20, 25 and 50 parts can be chosen by the mode select inputs. This is called “Fractional extension”. A similar extension called “Half channel offset” can be obtained in modes 2, 4, 6 and 8, if the JAM inputs are switched between zero and 1, 2, 3 and 4 respectfully. This is illustrated in Fig.5. This feature is used primarily in cases where radio channels are allocated according to the following formula: Channel frequency = channel spacing x (N + 0.5) N is an integer. Control inputs Kb and Kc can be used to initiate and lock the counter in the “master preset” mode. In this condition the flip-flops in the counter are preset in accordance with the JAM inputs and the counter remains in that mode as long as Kb and Kc both remain LOW. The counter begins to count down from the preset state when a counting mode other than the “master preset” mode is selected. Whenever the “master preset” mode is used, control signals Kb =Kc = LOW must be applied for at least 2 full clock pulses. After the “master preset” mode inputs have been changed to one of the counting modes, the next positive-going clock transition changes an internal flip-flop so that the count-down begins on the second positive-going clock transition. Thus, after a “master preset” mode, there is always one extra count before the output goes HIGH. Figure 6 illustrates the operation of the counter in the divide-by-8 mode starting from the preset state 3. If the “master preset” mode is started two clock cycles or less before an output pulse, the output pulse will appear at the correct moment. When the output pulse appears and the “master preset” mode is not selected, the counter is preset according to the states of the JAM inputs. When Ka, Kb, Kc and LE are LOW, the counter operates in the “preset inhibit” mode, during which the counter divides at a fixed rate of 10 000, independent of the state of the JAM inputs. However, the first cycle length after leaving the “master preset” mode is determined by the JAM inputs. When Ka, Kb and Kc are LOW and input LE = HIGH, the counter operates in the normal divide-by-10 mode, however, without the latch operation at the output. This device is particularly advantageous in digital frequency synthesizer circuits (VHF, UHF, FM, AM etc.) for communication systems, where programmable divide-by-”n” counters are an integral part of the synthesizer phase-locked-loop sub-system. The 74HC/HCT4059 can also be used to perform the synthesizer “fixed divide-by-n” counting function, as well as general purpose counting for instrumentation functions such as totalizers, production counters and “time out” timers. Schmitt-trigger action at the clock input makes the circuit highly tolerant to slower clock rise and fall times. |
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