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Notes: 1.

5. The rise and fall times specified here refer to the driver device and are part of general Hs-mode specification.

7. Cb is the capacitive load for each bus line.

9. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

Cb=100pF

25

ns

Cb=400pF

120

ns

Capacitive load for SDAH and

SCLH

100

400

pF

Capacitive load for SDAH + SDA

line and SCLH + SCL line

400

pF

note 5

10

ns

PARALLEL INTERFACE

Enable Cycle Time

125

ns

Enable Pulse width

60

ns

Address Set-up Time

30

ns

Address Hold Time

50

ns

Data Set-Up Time

30

ns

Data Hold Time

50

ns

SERIAL INTERFACE

Clock Frequency

8

MHz

5

MHz

Clock Cycle SCLK

125

ns

SCLK pulse width HIGH

70

ns

SCLK Pulse width LOW

70

ns

SCE setup time

50

ns

SCE hold time

50

ns

SCE minimum high time

60

ns

SCE start hold time

Note 8

60

ns

SD/C setup time

60

ns

SD/C hold time

40

ns

SDIN setup time

40

ns

SDIN hold time

40

ns

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

F

frame

f

osc

520

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ELECTRICAL CHARACTERISTICS (continued)