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WV3HG64M72EER534D6IMG Scheda tecnica(PDF) 7 Page - White Electronic Designs Corporation

Il numero della parte WV3HG64M72EER534D6IMG
Spiegazioni elettronici  512MB - 64Mx72 DDR2 SDRAM REGISTERED DIMM, w/PLL
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Produttore elettronici  WEDC [White Electronic Designs Corporation]
Homepage  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

WV3HG64M72EER534D6IMG Scheda tecnica(HTML) 7 Page - White Electronic Designs Corporation

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WV3HG64M72EER-D6
ADVANCED
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
August 2006
Rev. 1
AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Clock cycle time
CL = 6
tCK (6)
TBD
TBD
ps
CL = 5
tCK (5)
TBD
TBD
3,000
8,000
ps
CL = 4
tCK (4)
TBD
TBD
3,750
8,000
3,750
8,000
5,000
8,000
ps
CL = 3
tCK (3)
TBD
TBD
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
TBD
TBD
MIN
(tCH,tCL)
MIN
(tCH,tCL)
MIN
(tCH,tCL)ps
Clock jitter
tJIT
TBD
TBD
-125
125
-125
125
-125
125
ps
DQ output access time from CK/CK#
tAC
TBD
TBD
-450
+450
-500
+500
-600
+600
ps
Data-out high-impedance window from
CK/CK#
tHZ
TBD
TBD
tAC(MAX)
tAC(MAX)
tAC(MAX)
ps
Data-out low-impedance window from
CK/CK#
tLZ
TBD
TBD
tAC(MIN)
tAC(MAX)
tAC(MIN)
tAC(MAX)
tAC(MIN)
tAC(MAX)
ps
DQ and DM input setup time relative to
DQS
tDS
TBD
TBD
100
100
150
DQ and DM input hold time relative to DQS
tDH
TBD
TBD
225
225
275
DQ and DM input pulse width (for each
input)
tDIPW
TBD
TBD
0.35
0.35
0.35
tCK
Data hold skew factor
tQHS
TBD
TBD
340
400
450
ps
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
tQH
TBD
TBD
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
TBD
TBD
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
DQS input high pulse width
tDQSH
TBD
TBD
0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
TBD
TBD
0.35
0.35
0.35
tCK
DQS output access time from CK/CK#
tDQSCK
TBD
TBD
-400
+400
-450
+450
-500
+500
ps
DQS falling edge to CK rising … setup time
tDSS
TBD
TBD
0.2
0.2
0.2
tCK
DQS falling edge from CK rising … hold
time
tDSH
TBD
TBD
0.2
0.2
0.2
tCK
DQS…DQ skew, DQS to last DQ valid, per
group,
per access
tDQSQ
TBD
TBD
240
300
350
ps
DQS read preamble
tRPRE
TBD
TBD
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
TBD
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
tWPRES
TBD
TBD
000
ps
DQS write preamble
tWPRE
TBD
TBD
0.35
0.35
0.35
tCK
DQS write postamble
tWPST
TBD
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching
transition
tDQSS
TBD
TBD
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tCK
Address and control input pulse width for
each input
tIPW
TBD
TBD
0.6
0.6
0.6
tCK
Address and control input setup time
tIS
TBD
TBD
200
250
250
ps
Address and control input hold time
tIH
TBD
TBD
275
375
475
ps
Address and control input hold time
tCCD
TBD
TBD
222
tCK
* AC specification is based on
SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page


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