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WV3HG64M72EER-D7 Scheda tecnica(PDF) 6 Page - White Electronic Designs Corporation |
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WV3HG64M72EER-D7 Scheda tecnica(HTML) 6 Page - White Electronic Designs Corporation |
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6 / 11 page  WV3HG64M72EER-D7 February 2006 Rev. 2 PRELIMINARY 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DDR2 ICC SPECIFICATIONS AND CONDITIONS Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V Symbol Parameter Condition 806 665 534 403 Unit ICC0* Operating one bank active-precharge; tCK = tCK(DD); tRC = tRC(I CC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD TBD 1120 1120 mA ICC1* Operating one bank active-read- precharge; IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(I CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING; Data pattern is same as ICC4W. TBD TBD 1255 1255 mA ICC2P** Precharge power- down current; All banks idle; tCK = tCK(I CC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD TBD 472 472 mA ICC2Q** Precharge quite standby current; All banks idle; tCK = tCK(I CC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD TBD 670 670 mA ICC2N** Precharge standby current; All banks idle; tCK = tCK(I CC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING TBD TBD 715 715 mA ICC3P** Active power-down current; All banks open; tCK = tCK(I CC), CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 TBD TBD 670 670 mA Slow PDN Exit MRS(12) = 1 TBD TBD 508 508 mA ICC3N** Active standby current; All banks open; tCK = tCK(I CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD TBD 850 850 mA ICC4W* Operating burst write current; All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(I CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD TBD 1480 1390 mA ICC4R* Operating burst read current; All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(I CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W. TBD TBD 1525 1390 mA ICC5** Burst auto refresh current; tCK = tCK(I CC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD TBD 1660 1660 mA ICC6** Self refresh current; CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal TBD TBD 472 472 mA ICC7* Operating bank interleave read current; All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(I CC) - 1*tCK(I CC); tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING TBD TBD 2380 2380 mA Notes: ICC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. * Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition. |
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