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WV3HG64M64EEU665D6GG Scheda tecnica(PDF) 8 Page - White Electronic Designs Corporation |
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WV3HG64M64EEU665D6GG Scheda tecnica(HTML) 8 Page - White Electronic Designs Corporation |
8 / 11 page WV3HG64M64EEU-D6 December 2005 Rev. 0 ADVANCED 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC TIMING PARAMETERS (cont'd) 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V AC CHARACTERISTICS 806 665 534 403 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT Address and control input setup time tIS TBD TBD TBD 250 250 ps Address and control input hold time tIH TBD TBD TBD 375 475 ps CAS# to CAS# command delay tCCD TBD TBD TBD 22 tCK ACTIVE to ACTIVE (same bank) command tRC TBD TBD TBD 55 55 ns ACTIVE bank a to ACTIVE bank b command tRRD TBD TBD TBD 7.5 7.5 ns ACTIVE to READ or WRITE delay tRCD TBD TBD TBD 15 15 ns Four Bank Activate period tFAW TBD TBD TBD TBD 37.5 37.5 37.5 37.5 ACTIVE to PRECHARGE command tRAS TBD TBD TBD TBD 45 70,000 45 70,000 ns Internal READ to precharge command delay tRTP TBD TBD TBD 7.5 7.5 ns Write recovery time tWR TBD TBD TBD 15 15 ns Auto precharge write recovery + precharge time tDAL TBD TBD TBD tWR + tRP tWR + tRP ns Internal WRITE to READ command delay tWTR TBD TBD TBD 7.5 10 ns PRECHARGE command period tRP TBD TBD TBD 15 15 PRECHARGE ALL command period tRPA TBD TBD TBD tWR + tCK tWR + tCK ns LOAD MODE command cycle time tMRD TBD TBD TBD 22 tCK CKE low to CK,CK# uncertainty tDELAY TBD TBD TBD tIS + tCK + tIH tIS + tCK + tIH ns REFRESH to REFRESH command interval tRFC TBD TBD TBD TBD 127.5 70,000 127.5 70,000 ns Average periodic refresh interval tREFI TBD TBD TBD TBD 7.8 7.8 µs Exit self refresh to non-READ command tXSNR TBD TBD TBD tRFC (MIN) + 10 tRFC (MIN) + 10 ns Exit self refresh to READ command tXSRD TBD TBD TBD 200 200 tCK Exit self refresh timing reference tISXR TBD TBD TBD tIS tIS ps ODT turn-on delay tAOND TBD TBD TBD TBD 2222 tCK ODT turn-on tAON TBD TBD TBD TBD tAC (MIN) tAC (MAX) + 1000 tAC (MIN) tAC (MAX) + 1000 ps ODT turn-off delay tAOFD TBD TBD TBD TBD 2.5 2.5 2.5 2.5 tCK ODT turn-off tAOF TBD TBD TBD TBD tAC (MIN) tAC (MAX) + 600 tAC (MIN) tAC (MAX) + 600 ps ODT turn-on (power-down mode) tAONPD TBD TBD TBD TBD tAC (MIN) + 2000 2 x tCK + tAC (MAX) + 1000 tAC (MIN) + 2000 2 x tCK + tAC (MAX) + 1000 ps ODT turn-off (power-down mode) tAOFPD TBD TBD TBD TBD tAC (MIN) + 2000 2.5 x tCK + tAC (MAX) + 1000 tAC (MIN) + 2000 2.5 x tCK + tAC (MAX) + 1000 ps ODT to power-down entry latency tANPD TBD TBD TBD 33 tCK ODT power-down exit latency tAXPD TBD TBD TBD 88 tCK Exit active power-down to READ command, MR[bit12=0] tXARD TBD TBD TBD 22 tCK Exit active power-down to READ command, MR[bit12=1] tXARDS TBD TBD TBD 6 - AL 6 - AL tCK A Exit precharge power-down to any non-READ command. tXP TBD TBD TBD 22 tCK CKE minimum high/low time tCKE TBD TBD TBD 33 tCK NOTE: • AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. |
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