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WV3HG32M40SEU-PD4 Scheda tecnica(PDF) 8 Page - White Electronic Designs Corporation |
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WV3HG32M40SEU-PD4 Scheda tecnica(HTML) 8 Page - White Electronic Designs Corporation |
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8 / 11 page  WV3HG32M40SEU-PD4 June 2006 Rev. 2 ADVANCED 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC TIMING PARAMETERS (cont'd) AC CHARACTERISTICS 665 534 403 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNIT ACTIVE to ACTIVE (same bank) command tRC 55 55 55 ns ACTIVE bank a to ACTIVE bank b command tRRD 10 10 10 ns ACTIVE to READ or WRITE delay tRCD 15 15 15 ns Four Bank Activate period tFAW 50 50 50 ns ACTIVE to PRECHARGE command tRAS 45 70,000 45 70,000 40 70,000 ns Internal READ to precharge command delay tRTP 7.5 7.5 7.5 ns Write recovery time tWR 15 15 15 ns Auto precharge write recovery + precharge time tDAL tWR + tRP tWR + tRP tWR + tRP ns Internal WRITE to READ command delay tWTR 7.5 7.5 10 ns PRECHARGE command period tRP 15 15 15 ns PRECHARGE ALL command period tRPA tRP+tCK tRP+tCK tRP+tCK ns LOAD MODE command cycle time tMRD 222 tCK CKE low to CK,CK# uncertainty tDELAY tIS + tCK + tIH tIS + tCK + tIH tIS + tCK + tIH ns REFRESH to Active of Refresh to Refresh command interfal tRFC 105 70,000 105 70,000 105 70,000 ns Average periodic refresh interval tREFI 7.8 7.8 7.8 µs Exit self refresh to non-READ command tXSNR tRFC (MIN) + 10 tRFC (MIN) + 10 tRFC (MIN) + 10 ns Exit self refresh to READ command tXSRD 200 200 200 tCK Exit self refresh timing reference tISXR tIS tIS tIS ps ODT turn-on delay tAOND 222222 tCK ODT turn-on tAON tAC (MIN) tAC (MAX) + 700 tAC (MIN) tAC (MAX) + 1000 tAC (MIN) tAC (MAX) + 1000 ps ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 2.5 2.5 tCK ODT turn-off tAOF tAC (MIN) tAC (MAX) + 600 tAC (MIN) tAC (MAX) + 600 tAC (MIN) tAC (MAX) + 600 ps ODT turn-on (power-down mode) tAONPD tAC (MIN) + 2000 2 x tCK + tAC (MAX) + 1000 tAC (MIN) + 2000 2 x tCK + tAC (MAX) + 1000 tAC (MIN) + 2000 2 x tCK + tAC (MAX) + 1000 ps ODT turn-off (power-down mode) tAOFPD tAC (MIN) + 2000 2.5 x tCK + tAC (MAX) + 1000 tAC (MIN) + 2000 2.5 x tCK + tAC (MAX) + 1000 tAC (MIN) + 2000 2.5 x tCK + tAC (MAX) + 1000 ps ODT to power-down entry latency tANPD 333 tCK ODT power-down exit latency tAXPD 888 tCK Exit active power-down to READ command, MR[bit12=0] tXARD 222 tCK Exit active power-down to READ command, MR[bit12=1] tXARDS 7 - AL 6 - AL 6 - AL tCK A Exit precharge power-down to any non-READ command. tXP 222 tCK CKE minimum high/low time tCKE 333 tCK Note: AC specification is based on ELPIDA components. Other DRAM manufactures specification may be different. |
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