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74F175A Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74F175A Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74F175A Quad D flip-flop 2 1996 Mar 12 853–0047 16555 FEATURES • Four edge-triggered D-type flip-flops • Buffered common clock • Buffered asynchronous Master Reset • True and complementary outputs • Industrial temperature range available (–40°C to +85°C) • PNP light loading inputs DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. All Q outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where both true and complementary outputs are required, and the CP and MR are common to all storage elements. PIN CONFIGURATION 16 15 14 13 12 11 10 7 6 5 4 3 2 1 9 8 VCC SF00718 Q3 Q3 D3 D2 Q2 Q2 CP MR Q0 Q0 D0 D1 Q1 Q1 GND TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 74F175A 160MHz 22mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG. DWG. # 16-pin plastic DIP 74F175AN SOT38-4 16-pin plastic SO 74F175AD SOT109-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 – D3 Data inputs 74F175A 1.0/0.033 20 µA/20µA MR Master reset input (active–Low) 74F175A 1.0/0.033 20 µA/20µA CP Clock input (active rising edge) 74F175A 1.0/0.033 20 µA/20µA Q0–Q3 True outputs 50/33 1.0mA/20mA Q0–Q3 Complementary outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20 µA in the High state and 0.6mA in the Low state. |
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