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74ALVCH16825 Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74ALVCH16825 Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74ALVCH16825 18-bit buffer/driver (3-State) 2 1998 Jul 27 853-2097 19785 FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple V CC and GND pins for minimum noise and ground bounce • All data inputs have bus hold • Output drive capability 50Ω transmission lines @ 85°C DESCRIPTION The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with 3-State outputs for bus-oriented applications. The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals. For either 9-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be LOW for corresponding D outputs to be active. If either output enable input is HIGH, the outputs of that 9-buffer section are in the high impedance state. The 74ALVCH16825 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1OE1 1Y1 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 GND VCC GND 1Y7 1Y8 GND GND 2Y0 2Y1 GND 2Y2 2Y3 2Y4 VCC 2Y5 2Y6 GND 2Y7 2OE1 1A0 1A1 GND 1A2 1A3 VCC 1A4 1A5 1A6 GND 1A7 1A8 GND GND 2A0 2A1 GND 2A2 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2Y8 2OE2 1OE2 SH00139 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay CP to Qn VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF 2.0 2.0 ns CI Input capacitance 4.0 pF CPD Power dissipation capacitance per latch VI = GND to VCC1 Output enabled 19 pF CPD Power dissi ation ca acitance er latch VI = GND to VCC1 Output disabled 3 F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER 56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40 °C to +85°C 74ALVCH16825 DGG ACH16825 DGG SOT364-1 |
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