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74ALVCH16821 Scheda tecnica(PDF) 8 Page - NXP Semiconductors |
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74ALVCH16821 Scheda tecnica(HTML) 8 Page - NXP Semiconductors |
8 / 12 page Philips Semiconductors Product specification 74ALVCH16821 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 1998 May 29 8 AC WAVEFORMS VCC = 2.3 TO 2.7 V RANGE 1. VM = 0.5 V 2. VX = VOL + 0.15V 3. VY = VOH – 0.15V 4. VI = VCC 5. VOL and VOH are the typical output voltage drop that occur with the output load. VCC = 3.0 TO 3.6 V RANGE AND VCC = 2.7 V 1. VM = 1.5 V 2. VX = VOL + 0.3V 3. VY = VOH – 0.3V 4. VI = 2.7 V 5. VOL and VOH are the typical output voltage drop that occur with the output load. VM nCP INPUT nQn OUTPUT tw tPHL VM tPLH 1/fMAX VM VOH VOL SH00128 VI GND Waveform 1. The input (nCP) to output propagation delays. tPLZ tPZL VI nOE INPUT GND VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs enabled outputs disabled tPHZ VM VM VM tPZH VX VY SW00308 Waveform 2. The 3-State enable and disable times. nQn OUTPUT VM VM nDn INPUT SH00129 nCP INPUT VM GND VI GND VI VOL VOH tsu tsu th th Waveform 3. Set up and hold times. TEST CIRCUIT SWITCH POSITION PULSE GENERATOR RT VI D.U.T. VO CL VCC RL = 500 Ω Test Circuit for switching times Open GND S1 DEFINITIONS VCC VI < 2.7V VCC TEST S1 tPLH/tPHL Open RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. 2 < VCC tPLZ/tPZL 2.7V 2.7–3.6V tPHZ/tPZH GND RL = 500 Ω 2 * VCC SV00906 Waveform 4. Load circuitry for switching times |
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