Philips Semiconductors

Product specification

74ALVCH16373

16-bit D-type transparent latch (3-State)

1999 Sep 20

3

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

1

1OE

Output enable input

(active LOW)

2, 3, 5, 6, 8, 9,

11, 12

1Q0 to 1Q7

Data inputs/outputs

4, 10, 15, 21,

28, 34, 39, 45

GND

Ground (0V)

7, 18, 31, 42

Positive supply voltage

13, 14, 16, 17,

19, 20, 22, 23

2Q0 to 2Q7

Data inputs/outputs

24

2OE

Output enable input

(active LOW)

25

2LE

Latch enable input (active

HIGH)

36, 35, 33, 32,

30, 29, 27, 26

2D0 to 2D7

Data inputs

47, 46, 44, 43,

41, 40, 38, 37

1D0 to 1D7

Data inputs

48

1LE

Latch enable input (active

HIGH)

LOGIC SYMBOL

1OE

2OE

1LE

2LE

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

47

46

44

43

41

40

38

37

36

35

33

32

30

29

27

26

48

25

23

22

20

19

17

16

14

13

12

11

9

8

6

5

3

2

24

1

SW00067

LOGIC DIAGRAM

DQ

LE

LE

LATCH

1

1D0

1LE

1OE

1Q0

TO 7 OTHER CHANNELS

DQ

LE

LE

LATCH

9

2D0

2LE

2OE

2Q0

TO 7 OTHER CHANNELS

SW00068

FUNCTION TABLE (per section of eight bits)

OPERATING MODES

INPUTS

INTERNAL

OUTPUTS

OPERATING MODES

nOE

nLE

nDn

LATCHES

nQn

Enable and read register

(transparent mode)

L

L

H

H

L

H

L

H

L

H

Latch and read register

(hold mode)

L

L

L

L

l

h

L

H

L

H

Latch register and disable outputs

H

H

L

L

l

h

L

H

Z

Z

H = HIGH voltage level

h

= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition

L

= LOW voltage level

l

= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition

X = don’t care

Z = high impedance OFF-state