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74ALS564A Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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74ALS564A Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
4 / 12 page Philips Semiconductors Product specification 74ALS563A/74ALS564A Latch/flip-flop 1996 Jul 01 4 LOGIC DIAGRAM – 74ALS563A VCC = Pin 20 GND = Pin 10 D0 D E Q Q0 2 19 D1 D E Q Q1 3 18 D2 D E Q Q2 4 17 D3 D E Q Q3 5 16 D4 D E Q Q4 6 15 D5 D E Q Q5 7 14 D6 D E Q Q6 8 13 D7 D E Q Q7 9 12 11 E SC00116 1 OE FUNCTION TABLE – 74ALS563A INPUTS OUTPUTS INTERNAL OPERATING MODE OE E Dn REGISTER Q0 – Q7 OPERATING MODE L H L L H Enable and read register L H H H L Enable and read register L ↓ l L H Latch and read register L ↓ h H L Latch and read register L L X NC NC Hold H L X NC Z Disable outputs H H Dn Dn Z Disable outputs H = High voltage level h = High state must be present one setup time before the High-to-Low enable transition L = Low voltage level l = Low state must be present one setup time before the High-to-Low enable transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low enable transition |
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