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74AHCT138D Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74AHCT138D Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 16 page 1999 Sep 27 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74AHC138; 74AHCT138 FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT138 decoders accept three binary weighted address inputs (A0,A1 and A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The ‘138’ features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the ‘138’ to a 1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The ‘138’ is identical to the ‘238’ but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT AHC AHCT tPHL/tPLH propagation delay An to Yn CL = 15 pF; VCC = 5 V 4.4 4.4 ns propagation delay E3 to Yn; En to Yn CL = 15 pF; VCC = 5 V 4.2 4.3 ns CI input capacitance VI =VCC or GND 3.0 3.0 pF CO output capacitance 4.0 4.0 pF CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 18 23 pF |
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