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74AHC139 Scheda tecnica(PDF) 2 Page - NXP Semiconductors

Il numero della parte 74AHC139
Spiegazioni elettronici  Dual 2-to-4 line decoder/demultiplexer
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Produttore elettronici  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74AHC139 Scheda tecnica(HTML) 2 Page - NXP Semiconductors

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1999 Sep 01
2
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74AHC139;
74AHCT139
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt trigger actions
• Inputs accept voltages higher than VCC
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT139 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT139 are high-speed, dual 2-to-4 line
decoder/demultiplexers.
This device has two independent decoders, each
accepting two binary weighted inputs (nA0 and nA1) and
providing four mutually exclusive active LOW outputs
(nY0 to nY3). Each decoder has an active LOW enable
input (nE). When nE is HIGH, every output is forced HIGH.
The enable input can be used as the data input for a 1-to-4
demultiplexer application.
The ‘139’ is identical to the HEF4556 of the HE4000B
family.
QUICK REFERENCE DATA
Ground = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
CL = 15 pF; VCC =5V
nAn to nYn
3.9
4.7
ns
nEtonYn
3.4
3.6
ns
CI
input capacitance
VI =VCC or GND
3.0
3.0
pF
CO
output capacitance
4.0
4.0
pF
CPD
power dissipation capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
25.76
22.36
pF


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