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74ABT834D Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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74ABT834D Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
7 / 7 page Philips Semiconductors Advanced BiCMOS Products Objective specification 74ABT834 Octal inverting transceiver with parity generator/checker (3–State) June 9, 1992 7 TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS Load resistor ( Ω) 0 2 4 6 8 10 12 14 16 18 0 100 200 300 400 500 600 tPLH tPHL NOTE: When using Open–Collector parts, the value of the pull–up resistor greatly affects the value of the tPLH. For example, changing the specified pull–up resistor value from 500 Ω to 100Ω will improve the tPLH over 300% with only a slight change in the tPHL. However, if the value of the pull–up resistor is changed, the user must make certain that the total IOL current through the resistor and the total IIL’s of the receivers does not exceed the IOL maximum specification. TEST CIRCUIT AND WAVEFORM LOAD VALUES OUTPUT RX VX ERROR 100 Ω VCC All other 500 Ω 7.0V PULSE GENERATOR RT VIN D.U.T VOUT CL RL VCC RX VX Test Circuit for 3–State Outputs VM VM tW AMP (V) NEGATIVE PULSE 10% 10% 90% 90% 0V VM VM tW AMP (V) POSITIVE PULSE 90% 90% 10% 10% 0V tTHL (tF) tTLH (tR) tTHL (tF) tTLH (tR) VM = 1.5V Input Pulse Definition DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude Rep. Rate tW tR tF 74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open |
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