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GS816118BD-150I Scheda tecnica(PDF) 4 Page - GSI Technology |
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GS816118BD-150I Scheda tecnica(HTML) 4 Page - GSI Technology |
4 / 35 page TQFP Pin Description Symbol Type Description A0, A1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins NC — No Connect BW I Byte Write—Writes all enabled bytes; active low BA, BB, BC, BD I Byte Write Enable for DQA, DQB Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E1 I Chip Enable; active low G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply GS816118B(T/D)/GS816132B(D)/GS816136B(T/D) Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03 9/2005 4/35 © 2004, GSI Technology |
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