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GS832436B-225I Scheda tecnica(PDF) 1 Page - GSI Technology |
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GS832436B-225I Scheda tecnica(HTML) 1 Page - GSI Technology |
1 / 46 page Rev: 1.00 10/2001 1/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology). Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs 250 MHz–133MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 119- and 209-Pin BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable (x36 and x72) • Dual Cycle Deselect only (x18) • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x36/x72 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119- and 209-bump BGA package Functional Description Applications The GS832418/36/72 is a 37,748,736-bit high performance 2-die synchronous SRAM module with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge- triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. SCD and DCD Pipelined Reads The GS832436(B/C) and the GS832472(C) are SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAMs. The GS832418(B/C) is a DCD-only SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure the x36 or x72 versions of this SRAM for either mode of operation using the SCD mode input. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS832418/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. -250 -225 -200 -166 -150 -133 Unit Pipeline 3-1-1-1 tKQ tCycle 2.3 4.0 2.5 4.4 3.0 5.0 3.5 6.0 3.8 6.6 4.0 7.5 ns ns 3.3 V Curr (x18) Curr (x36) Curr (x72) 365 560 660 335 510 600 305 460 540 265 400 460 245 370 430 215 330 380 mA mA mA 2.5 V Curr (x18) Curr (x36) Curr (x72) 360 550 640 330 500 590 305 460 530 260 390 450 240 360 420 215 330 370 mA mA mA Flow Through 2-1-1-1 tKQ tCycle 6.0 7.0 6.5 7.5 7.5 8.5 8.5 10 10 10 11 15 ns ns 3.3 V Curr (x18) Curr (x36) Curr (x72) 235 300 350 230 300 350 210 270 300 200 270 300 195 270 300 150 200 220 mA mA mA 2.5 V Curr (x18) Curr (x36) Curr (x72) 235 300 340 230 300 340 210 270 300 200 270 300 195 270 300 145 190 220 mA mA mA |
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