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GS832018T-150IV Scheda tecnica(PDF) 5 Page - GSI Technology

Il numero della parte GS832018T-150IV
Spiegazioni elettronici  2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
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Produttore elettronici  GSI [GSI Technology]
Homepage  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS832018T-150IV Scheda tecnica(HTML) 5 Page - GSI Technology

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TQFP Pin Description
Symbol
Type
Description
A0, A1
I
Address field LSBs and Address Counter preset Inputs
A
I
Address Inputs
DQA
DQB1
DQC
DQD
I/O
Data Input and Output pins
NC
No Connect
BW
I
Byte Write—Writes all enabled bytes; active low
BA, BB
I
Byte Write Enable for DQA, DQB Data I/Os; active low
BC, BD
I
Byte Write Enable for DQC, DQD Data I/Os; active low
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable—Writes all bytes; active low
E1, E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
GS832018/32/36T-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 6/2006
5/24
© 2003, GSI Technology


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