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GS8322ZV18GE-133 Scheda tecnica(PDF) 3 Page - GSI Technology |
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GS8322ZV18GE-133 Scheda tecnica(HTML) 3 Page - GSI Technology |
3 / 39 page GS8322ZV18(B/E)/GS8322ZV36(B/E)/GS8322ZV72(C) Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03a 2/2006 3/39 © 2002, GSI Technology GS8322ZV72 209-Bump BGA Pin Description Symbol Type Description A0, A1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD DQE DQF DQG DQH I/O Data Input and Output pins BA, BB I Byte Write Enable for DQA, DQB I/Os; active low BC,BD I Byte Write Enable for DQC, DQD I/Os; active low BE, BF, BG,BH I Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low NC — No Connect CK I Clock Input Signal; active high E1 I Chip Enable; active low E3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low MCH I Must Connect High MCH I Must Connect High MCL Must Connect Low W I Write Enable; active low ZQ I FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive] CKE I Clock Enable; active low |
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