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GS8321Z36GE-166V Scheda tecnica(PDF) 5 Page - GSI Technology |
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GS8321Z36GE-166V Scheda tecnica(HTML) 5 Page - GSI Technology |
5 / 32 page GS8321Z18/32/36E-xxxV Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.05 6/2006 5/32 © 2003, GSI Technology GS8321Z18/32/36E-xxxV 165-Bump BGA Pin Description Symbol Type Description A0, A1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I Clock Input Signal; active high CKE I Clock Enable; active low W I Write Enable; active low E1 I Chip Enable; active low E3 I Chip Enable; active low E2 I Chip Enable; active high FT I Flow Through / Pipeline Mode Control G I Output Enable; active low ADV I Burst address counter advance enable; active high ZZ I Sleep mode control; active high LBO I Linear Burst Order mode; active low TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCH — Must Connect High VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply |
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