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GS8180Q18D-133 Scheda tecnica(PDF) 11 Page - GSI Technology |
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GS8180Q18D-133 Scheda tecnica(HTML) 11 Page - GSI Technology |
11 / 32 page GS8180Q18/36D-200/167/133/100* Rev: 2.03 10/2004 11/32 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Separate I/O Burst of 2 SigmaQuad SRAM Read Truth Table AR Output Next State Q Q K ↑ (tn) K ↑ (tn) K ↑ (tn) K ↑ (tn+1) K ↑ (tn+1½) X 1 Deselect Hi-Z Hi-Z V 0 Read Q0 Q1 Notes: 1. X = Don’t Care, 1 = High, 0 = Low, V = Valid. 2. R is evaluated on the rising edge of K. 3. Q0 and Q1 are the first and second data output transfers in a read. Separate I/O Burst of 2 SigmaQuad SRAM Write Truth Table AW BWn BWn Input Next State D D K ↑ (tn + ½) K ↑ (tn) K ↑ (tn) K ↑ (tn + ½) K ↑, K ↑ (tn), (tn + ½) K ↑ (tn) K ↑ (tn + ½) V 0 0 0 Write Byte Dx0, Write Byte Dx1 D0 D1 V 0 0 1 Write Byte Dx0, Write Abort Byte Dx1 D0 X V 0 1 0 Write Abort Byte Dx0, Write Byte Dx1 X D1 X 0 1 1 Write Abort Byte Dx0, Write Abort Byte Dx1 X X X 1 X X Deselect X X Notes: 1. X = Don’t Care, H = High, L = Low, V = Valid. 2. W is evaluated on the rising edge of K. 3. D0 and D1 are the first and second data input transfers in a write. 4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.). x18 Byte Write Enable (BWn) Truth Table BW0 BW1 D0–D8 D9–D17 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In |
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