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GS8162Z72C-133 Scheda tecnica(PDF) 5 Page - GSI Technology |
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GS8162Z72C-133 Scheda tecnica(HTML) 5 Page - GSI Technology |
5 / 31 page GS8162Z72C Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.22 11/2005 5/31 © 1999, GSI Technology Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. |
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