Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

GS840FH32AGT-12I Scheda tecnica(PDF) 1 Page - GSI Technology

Il numero della parte GS840FH32AGT-12I
Spiegazioni elettronici  256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  GSI [GSI Technology]
Homepage  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS840FH32AGT-12I Scheda tecnica(HTML) 1 Page - GSI Technology

  GS840FH32AGT-12I Datasheet HTML 1Page - GSI Technology GS840FH32AGT-12I Datasheet HTML 2Page - GSI Technology GS840FH32AGT-12I Datasheet HTML 3Page - GSI Technology GS840FH32AGT-12I Datasheet HTML 4Page - GSI Technology GS840FH32AGT-12I Datasheet HTML 5Page - GSI Technology GS840FH32AGT-12I Datasheet HTML 6Page - GSI Technology GS840FH32AGT-12I Datasheet HTML 7Page - GSI Technology GS840FH32AGT-12I Datasheet HTML 8Page - GSI Technology GS840FH32AGT-12I Datasheet HTML 9Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 21 page
background image
GS840FH18/32/36AT-8/8.5/10/12
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
8 ns–12 ns
3.3 V VDD
3.3 V and 2.5 V I/O
TQFP
Commercial Temp
Industrial Temp
Rev: 1.07 10/2004
1/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Flow Through mode operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS840FH18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS840FH18/32/36A is
available in a JEDEC-standard 100-lead TQFP package.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC standard for Burst RAMs calls for a FT mode pin
option (Pin 14 on TQFP). Board sites for flow through Burst
RAMs should be designed with VSS connected to the FT pin
location to ensure the broadest access to multiple vendor
sources. Boards designed with FT pin pads tied low may be
stuffed with GSI’s pipeline/flow through-configurable Burst
RAMs or any vendor’s flow through or configurable Burst
SRAM. Bumps designed with the FT pin location tied high or
floating must employ a non-configurable flow through Burst
RAM, (e.g., GS840FH18/32/36A), to achieve flow through
functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS840FH18/32/36A operates on a 3.3 V power supply
and all inputs/outputs are 3.3 V- and 2.5 V-compatible.
Separate output power (VDDQ) pins are used to decouple
output noise from the internal circuit.
Parameter Synopsis
-8
-8.5
-10
-12
Flow
Through
2-1-1-1
tKQ
tCycle
IDD
8 ns
9 ns
210 mA
8.5 ns
10 ns
190 mA
10 ns
12 ns
165 mA
12 ns
15 ns
135 mA


Codice articolo simile - GS840FH32AGT-12I

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
GSI Technology
GS840F18AGT-10 GSI-GS840F18AGT-10 Datasheet
554Kb / 21P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-10I GSI-GS840F18AGT-10I Datasheet
554Kb / 21P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-12 GSI-GS840F18AGT-12 Datasheet
554Kb / 21P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-12I GSI-GS840F18AGT-12I Datasheet
554Kb / 21P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-7.5 GSI-GS840F18AGT-7.5 Datasheet
554Kb / 21P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
More results

Descrizione simile - GS840FH32AGT-12I

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
GSI Technology
GS840E18T GSI-GS840E18T Datasheet
631Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840H18AT GSI-GS840H18AT Datasheet
747Kb / 30P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84018T GSI-GS84018T Datasheet
629Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840E18AT GSI-GS840E18AT Datasheet
762Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AT GSI-GS840F18AT Datasheet
554Kb / 21P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84018 GSI-GS84018 Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS880E18BT GSI-GS880E18BT Datasheet
645Kb / 28P
   512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88018T GSI-GS88018T Datasheet
1Mb / 25P
   512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
GS88018AT-250 GSI-GS88018AT-250 Datasheet
756Kb / 26P
   512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88036CGT-200 GSI-GS88036CGT-200 Datasheet
263Kb / 24P
   512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com