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GS841Z18AT-150 Scheda tecnica(PDF) 1 Page - GSI Technology |
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GS841Z18AT-150 Scheda tecnica(HTML) 1 Page - GSI Technology |
1 / 30 page GS841Z18/36AT-180/166/150/100 4Mb Pipelined and Flow Through Synchronous NBT SRAMs 180 MHz–100 MHz 3.3 V VDD 2.5 V and 3.3 V VDDQ 100-Pin TQFP Commercial Temp Industrial Temp Rev: 1.02 11/2004 1/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Features • 256K x 18 and 128K x 36 configurations • User-configurable Pipelined and Flow Through mode • NBT (No Bus Turn Around) functionality allows zero wait • Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • IEEE 1149.1 JTAG-compatible Boundary Scan • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleave Burst mode • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • Clock Control, registered, address, data, and control • ZZ Pin for automatic power-down • JEDEC-standard 100-lead TQFP package • Pb-Free 100-lead TQFP package available Functional Description The GS841Z18/36AT is a 4Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS841Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge- triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS841Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDEC- Standard 100-pin TQFP package. Parameter Synopsis –180 –166 –150 –100 Pipeline 3-1-1-1 tCycle tKQ IDD 5.5 ns 3.2 ns 335 mA 6.0 ns 3.5 ns 310 mA 6.6 ns 3.8 ns 280 mA 10 ns 4.5 ns 190 mA Flow Through 2-1-1-1 tKQ tCycle IDD 8 ns 9.1 ns 210 mA 8.5 ns 10 ns 190 mA 10 ns 12 ns 165 mA 12 ns 15 ns 135 mA |
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