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KM681000CLTI-7L Scheda tecnica(PDF) 1 Page - Samsung semiconductor |
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KM681000CLTI-7L Scheda tecnica(HTML) 1 Page - Samsung semiconductor |
1 / 10 page PRELIMINARY KM681000C Family CMOS SRAM Revision 2.0 November 1997 1 Document Title 128K x8 bit Low Power CMOS Static RAM Revision History Revision No. 0.0 0.1 1.0 2.0 Remark Design target Preliminary Final Final History Initial draft First revision - Seperate read and write at ICC, ICC1 ICC = ICC1 → Read : 15mA, Write : 35mA Finalized - Add 70ns speed bin for commercial product and 85ns speed bin for industrial. Revised - Improved operating current Add typical value. ICC Read : 15mA → 10mA(Remove write current) ICC2 : 90mA → 60mA - Speed bin change Remove 45ns from commercial part Remove 55ns and 100ns from industrial part. Draft Date November 22, 1995 April 15, 1996 September 5, 1996 November 5, 1997 The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. |
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