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TSL1301 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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TSL1301 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 8 page TSL1301 102 × 1 LINEAR SENSOR ARRAY WITH HOLD SOES031A – NOVEMBER 1996 – REVISED MAY 1997 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL DESCRIPTION NAME NO. DESCRIPTION AO 3 Analog output CLK 2 Clock. The clock controls charge transfer, pixel output, and reset. GND 6, 7 Ground (substrate). All voltages are referenced to the substrate. NC 5, 8 No internal connection SI 1 Serial input. SI defines the start of the data-out sequence. VDD 4 Supply voltage. Supply voltage for both analog and digital circuits. detailed description The sensor consists of 102 photodiodes, also called pixels, arranged in a linear array. Light energy impinging on a pixel generates photocurrent, which is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 102-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. This causes all 102 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. Then the next integration period begins. Note that a total 103 clock cycles are required, the 103rd cycle being necessary to terminate the output of pixel 102 and return the output to a high-impedance state, and to clear the internal shift register. AO is driven by a source follower that requires an external pulldown resistor. When the output is not in the output phase, it is in a high-impedance state. The output is nominally 0 V for no light input and 2 V for a nominal full-scale output. |
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