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STA-5063 Scheda tecnica(PDF) 2 Page - List of Unclassifed Manufacturers

Il numero della parte STA-5063
Spiegazioni elettronici  3.3 - 6.2 GHz General Purpose 3.3V 15dBm Amplifier
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303 S. Technology Court
Phone: (800) SMI-MMIC
http://www.sirenza.com
Broomfield, CO 80021
2
EDS-102990 Rev D
STA-5063 3.3-6.2GHz 15dBm Amplifier
Pin Out Description
Pin #
Function
Description
1
RFIN / VPC
RF input pin and power up down control. Supply VPC = 3.3V thru a 4.7Kohm resistor to this pin. For more
gain (~0.3dB), a 5.6nH inductor can also be used in place of the resistor. If an inductor is used, move the 4.7k
resistor towards the DC supply, but still in series with pin1. A minimum 1k series resitance is required on this
pin from the DC supply. VPC less than 2V shuts off the amplifier.
2,5,6
Ground
Put GND vias as close as possible to these pins. It is recommended to use the via pattern in out eval board
layout and recommended land pattern
3VCC
This provides Vcc to the active bias circuit and supplies the Vcc1 collector voltage of the first stage. This pin
needs to be bypassed with capacitors as close as possible to the pin. Two 0402 100pF capacitors are recom-
mended in parallel to lower the inductance to GND thru the caps.
4
RFOUT
Rf output for the amplifier and Vcc2 for the second stage.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Simplified Device Schematic
Absolute Maximum Ratings
Parameters
Value
Unit
ESD Rating (HBM)
1000
V
Total Device Current (I)
80
mA
Device Voltage (Pins 1 and 3)
4
V
Device Voltage (Pin 4)
5.5
V
Power Dissipation
0.40
W
Operating Lead Temperature (TL)
-40 to +85
ºC
RF Input Power
15
dBm
Storage Temperature Range
-40 to +150
ºC
Operating Junction Temperature (TJ)
+150
ºC
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation
the device voltage and current must not exceed the maximum
operating values specified in the table on page one.
Bias conditions should also satisfy the following expression:
IDVD < (TJ - TL) / RTH’ j-l
Active Bias
PIN 1
PIN 2
PIN 5
PIN 6
PIN 3
PIN 4


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