GS4910BCNE3 datasheet(11/113 Pages) GENNUM

Il numero della parte	GS4910BCNE3

Spiegazioni elettronici	HD/SD/Graphics Clock and Timing Generator with GENLOCK

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Produttore elettronici	GENNUM [Gennum Corporation]

Homepage	http://www.gennum.com

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11 / 113 page

GS4911B/GS4910B Data Sheet

36655 - 2

April 2006

11 of 113

12

ANALOG_GND

–

Power

Supply

Ground connection for the analog input block. Connect to GND.

13

AUD_PLL_GND

(GS4911B only)

–

Power

Supply

Ground connection for the audio clock synthesis internal block. Connect

to GND.

ANALOG_GND

(GS4910B only)

–

Power

Supply

Ground connection for the analog input block. Connect to GND.

14

AUD_PLL_VDD

(GS4911B only)

–

Power

Supply

Most positive power supply connection for the audio clock synthesis

internal block. Connect to +1.8V DC.

ANALOG_GND

(GS4910B only)

–

Power

Supply

Ground connection for the analog input block. Connect to GND.

15

10FID

Non

Synchronous

Input

REFERENCE SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

The 10FID external reference signal is applied to this pin by the

application layer. 10FID defines the field in which the video and audio

clock phase relationship is defined according to SMPTE 318-M. It is also

used to define a 3:2 video cadence.

NOTE: If the input reference format does not include a 10 Field ID signal,

this pin should be held LOW. See Section 3.4.2 on page 44.

16

HSYNC

Non

Synchronous

Input

REFERENCE SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

The HSYNC external reference signal is applied to this pin by the

application layer. When the GS4911B/GS4910B is operating in Genlock

mode, the device senses the polarity of the HSYNC input automatically,

and references to the leading edge.

If the user wishes to select one of the pre-programmed video and/or

timing output signals provided by the device, then this signal must

adhere to one of the 36 defined video or 16 different graphics display

standards supported by the device. In this mode of operation, the

HSYNC input provides a horizontal scanning reference signal.

The HSYNC signal may have analog timing, such as from a sync

separator, or may be digital such as from an SDI deserializer. Section 1.4

on page 20 describes the 36 video formats and 16 graphic formats

recognized by the GS4911B/GS4910B.

17

VSYNC

Non

Synchronous

Input

REFERENCE SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

The VSYNC external reference signal is applied to this pin by the

application layer. When the GS4911B/GS4910B is operating in Genlock

mode, the device senses the polarity of the VSYNC input automatically,

and references to the leading edge.

If the user wishes to select one of the pre-programmed video and/or

timing output signals provided by the device, then this signal must

adhere to one of the 36 defined video or 16 different graphics display

standards supported by the device. In this mode of operation, the

VSYNC input provides a vertical scanning reference signal.

The VSYNC signal may have analog timing, such as from a sync

separator, or may be digital such as from an SDI deserializer. Section 1.4

on page 20 describes the 36 video formats and 16 graphic formats

recognized by the GS4911B/GS4910B.

Table 1-1: Pin Descriptions (Continued)

Number

Name

Timing

Type

Description

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