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TDA7376PD Scheda tecnica(PDF) 5 Page - STMicroelectronics |
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TDA7376PD Scheda tecnica(HTML) 5 Page - STMicroelectronics |
5 / 9 page 5/9 TDA7376PD ELECTRICAL CHARACTERISTCS (Refer to the test circuits figgs 1 and 2, VS = 14.4V; RL = 4 Ω; f = 1KHz; Tamb = 25°C, unless otherwise specified). (*) Saturated square wave output (**) see figure 5 for THD setting. The TDA7376PD is equipped with a programmable clipping distortion detector circuitry that allows to sig- nal out the output stage saturation by providing a current sinking into an open collector output (DDout) when the total harmonic distortion of the output signal reaches the preset level. The desired threshold is fixed through an external divider that produces a proper voltage level across the THD set pin. Fig. 4 shows the THD detection threshold versus the THD set voltage. Since it is essential that the THD set voltage be proportional to the supply voltage, fig. 5 shows its value as a fraction of VCC. The actual voltage can be computed by multiplying the fraction corresponding to the desired THD threshold by the application’s sup- ply voltage. Symbol Parameter Test Condition Min. Typ. Max. Unit VS Supply Voltage Range 8 18 V Id Total Quiescent Drain Current RL = ∞ 200 mA VOS Output Offset Voltage 120 mV PO Output Power THD = 10%; THD = 10%; RL = 2 Ω 23 33 25 37 W W PO max Max. Output Power (*) 36 40 W PO EIAJ EIAJ Outout Power (*) VS = 13.7V 32 35 W THD Distortion PO = 0.5 to 10W PO = 0.5 to 15W 0.03 0.08 % % CT Cross Talk f = 1KHz; Rg f = 10KHz; Rg 80 70 dB dB RIN Input Impedance differential input Single Ended input 45 40 K Ω K Ω GV Voltage Gain differential input 25 26 27 dB Single Ended input 25 26 27 dB ∆GV Channel Gain Balance 1 dB EIN Input Noise Voltage Rg = 600 Ω; "A" weighted Rg = 600 Ω; 22Hz to 33KHz 3 46 µV µV SVR Supply Voltage Rejection f = 100Hz; Vr = 1Vrms; Rg = 0; f = 10Hz; Vr = 1Vrms; Rg = 0; 45 55 dB dB BW Power Bandwidth (-3dB) 75 kHz CMRR Common Mode Rejection Ratio VCM = 1Vrms input referred 60 dB ASB Stand-by Attenuation VSB = 1.5V; PO ref = 1W 80 90 dB VSB IN Stand-by In Threshold 1.5 V VSB OUT Stand-by Out Threshold 3.5 V Isb Stand-by Current Consumption VSB = 0V 20 µA AM Mute Attenuation VM = 1.5V; POref = 1W 85 dB VM IN Mute in Threshold 1.5 V VM OUT Mute out Threshold 3.5 V I6 Mute pin Current V6 = 0 to VS, ; VS max. = 18V 100 µA DDL Distortion Detection Level (**) 3.5 % DDOUT Distortion Detector Output DC Current Output low, sinked current (Vpin10 = 1.5V) 1mA Output high, leakage current (Vpin10 = VS, @ VSmax = 18V) 10 µA |
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