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KM68U1000C Scheda tecnica(PDF) 5 Page - Samsung semiconductor |
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KM68U1000C Scheda tecnica(HTML) 5 Page - Samsung semiconductor |
5 / 11 page K6T1008V2C, K6T1008U2C Family CMOS SRAM Revision 2.0 November 1997 5 CL1) 1. Including scope and jig capacitance AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL AC CHARACTERISTICS (Commercial product:TA=0 to 70°C, Extended product:TA=-25 to 85°C, Industrial product: TA=-40 to 85°C K6T1008V2C Family: Vcc=3.0~3.6V, K6T1008U2C Family: Vcc=2.7~3.3V) Parameter List Symbol Speed Bins Units 70ns 85ns 100ns Min Max Min Max Min Max Read Read cycle time tRC 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO1, tCO2 - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 25 0 25 0 30 ns Output disable to high-Z output tOHZ 0 25 0 25 0 30 ns Output hold from address change tOH 10 - 15 - 15 - ns Write Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 55 - 60 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 30 0 30 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns DATA RETENTION CHARACTERISTICS 1. CS1 ≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V Item Symbol Test Condition1) Min Typ Max Unit Vcc for data retention VDR CS11) ≥Vcc-0.2V 2.0 - 3.6 V Data retention current IDR Vcc=3.0V, CS1 ≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V - 0.3 5 µA Data retention set-up time tSDR See data retention waveform 0 - - ms Recovery time tRDR 5 - - |
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