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AD9887AKS-100 Scheda tecnica(PDF) 1 Page - Analog Devices |
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AD9887AKS-100 Scheda tecnica(HTML) 1 Page - Analog Devices |
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1 / 44 page  REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9887A Dual Interface for Flat Panel Displays FEATURES Analog Interface 170 MSPS Maximum Conversion Rate Programmable Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 170 MSPS 3.3 V Power Supply Full Sync Processing Midscale Clamping 4:2:2 Output Format Mode Digital Interface DVI 1.0 Compatible Interface 170 MHz Operation (2 Pixel/Clock Mode) High Skew Tolerance of 1 Full Input Clock Sync Detect for “Hot Plugging” Supports High Bandwidth Digital Content Protection APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Micro Displays Digital TVs FUNCTIONAL BLOCK DIAGRAM HSYNC COAST CLAMP CKINV CKEXT FILT VSYNC SERIAL REGISTER AND POWER MANAGEMENT SCL SDA A1 A0 2 DATACK HSOUT VSOUT SOGOUT Rx0+ Rx0– Rx1+ Rx1– Rx2+ Rx2– RxC+ RxC– RTERM DVI RECEIVER 8 8 8 ROUTA ROUTB 8 8 8 GOUTA GOUTB 8 8 8 BOUTA BOUTB 2 DATACK DE AD9887A DIGITAL INTERFACE ROUTA ROUTB GOUTA GOUTB BOUTA BOUTB HSOUT VSOUT SOGOUT DE DATACK 8 SYNC PROCESSING AND CLOCK GENERATION CLAMP RAIN CLAMP GAIN CLAMP BAIN A/D 8 8 8 ROUTA ROUTB A/D 8 8 8 GOUTA GOUTB A/D 8 8 8 BOUTA BOUTB ANALOG INTERFACE SCDT REFIN REF REFOUT DDCSCL DDCSDA MCL MDA HDCP SOGIN M U X E S 8 8 8 8 8 2 HSOUT VSOUT GENERAL DESCRIPTION The AD9887A offers designers the flexibility of an analog interface and digital visual interface (DVI) receiver integrated on a single chip. Also included is support for High Bandwidth Digital Content Protection (HDCP). The AD9887A is software and pin-to-pin compatible with the AD9887. Analog Interface The AD9887A is a complete 8-bit 170 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 330 MHz supports resolutions up to UXGA (1600 × 1200 at 60 Hz). The analog interface includes a 170 MHz triple ADC with internal 1.25 V reference, a phase-locked loop (PLL), and pro- grammable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC. Three- state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9887A’s on-chip PLL generates a pixel clock from HSYNC. Pixel clock output frequencies range from 12 MHz to 170 MHz. PLL clock jitter is typically 500 ps p-p at 170 MSPS. The AD9887A also offers full sync processing for composite sync and sync-on-green (SOG) applications. Digital Interface The AD9887A contains a DVI 1.0 compatible receiver and supports display resolutions up to UXGA (1600 1200 at 60 Hz). The receiver operates with true color (24-bit) panels in 1 or 2 pixel(s)/clock mode and features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9887A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.0 protocol. Fabricated in an advanced CMOS process, the AD9887A is provided in a 160-lead MQFP surface-mount plastic package and is specified over the 0 °C to 70°C temperature range. |
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