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FAN6520B Scheda tecnica(PDF) 10 Page - Fairchild Semiconductor

Il numero della parte FAN6520B
Spiegazioni elettronici  Single Synchronous Buck PWM Controller
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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FAN6520B Rev. 1.0.3
PLDRV is dissipation of the lower FET driver.
PLDRV = PL(R) × PL(F)
(10)
Where PH(R) and PH(F) are internal dissipations for the
rising and falling edges, respectively:
where:
PQ2 = QG2 × VGS(Q2) × FSW
(13)
Power MOSFET Selection
For more information on MOSFET selection for synchro-
nous buck regulators, refer to: AN-6005: Synchronous
Buck MOSFET Loss Calculations.
This Fairchild app note is located at:
http://www.fairchildsemi.com/an/AN/AN-6005.pdf
Losses in a MOSFET are the sum of its switching (PSW)
and conduction (PCOND) losses.
In typical applications, the FAN6520B converter's output
voltage is low with respect to its input voltage, therefore
the lower MOSFET (Q2) is conducting the full load cur-
rent for most of the cycle. Therefore choose a MOSFET
for Q2 which has low RDS(ON) to minimize conduction
losses.
In contrast, the high-side MOSFET (Q1) has a much
shorter duty cycle, and its conduction loss will therefore
have less of an impact. Q1, however, sees most of the
switching losses, so Q1’s primary selection criteria
should be gate charge.
High-Side Losses
Figure 9 shows a MOSFET’s switching interval, with the
upper graph being the voltage and current on the Drain
to Source and the lower graph detailing VGS vs. time with
a constant current charging the gate. The x-axis, there-
fore, is also representative of gate charge (QG) . CISS =
CGD + CGS, and it controls t1, t2, and t4 timing. CGD
receives the current from the gate driver during t3 (as
VDS is falling). The gate charge (QG) parameters on the
lower graph are either specified or can be derived from
the MOSFET’s datasheet.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1’s switching losses,
occur during the shaded time when the MOSFET has
voltage across it and current through it.
These losses are given by:
PUPPER = PSW + PCOND
where:
PUPPER is the upper MOSFET’s total losses, and PSW
and PCOND are the switching and conduction losses for a
given MOSFET. RDS(ON) is at the maximum junction tem-
perature (TJ). tS is the switching period (rise or fall time)
and is t2+t3 (Figure 9).
The driver’s impedance and CISS determine t2 while t3’s
period is controlled by the driver’s impedance and QGD.
Since most of tS occurs when VGS = VSP we can use a
constant current assumption for the driver to simplify the
calculation of tS:
Figure 9. Switching Losses and QG
Figure 10. Drive Equivalent Circuit
P
LR
()
P
Q2
R
LUP
R
LUP
R
E
R
G
++
-------------------------------------------
×
=
(11)
P
LF
()
P
Q2
R
LDN
R
HDN
R
E
R
G
++
--------------------------------------------
×
=
(12)
P
SW
V
DS
I
L
×
2
---------------------
2
×
t
s
×

 F
SW
=
(14)
P
COND
V
OUT
V
IN
--------------

 I
OUT
2
×
R
DS ON
()
×
=
(15)
V
SP
t1
t2
t3
4.5V
t4
t5
Q
G(SW)
V
DS
I
D
Q
GS
Q
GD
V
TH
V
GS
C
ISS
C
GD
C
ISS
C
GD
R
D
R
GATE
CGS
HDRV
5V
SW
VIN
G


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