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IDT74LVC138A Scheda tecnica(PDF) 1 Page - Integrated Device Technology |
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IDT74LVC138A Scheda tecnica(HTML) 1 Page - Integrated Device Technology |
1 / 6 page INDUSTRIALTEMPERATURERANGE IDT74LVC138A 3.3VCMOS3-LINE TO 8-LINE DECODER/DEMULTIPLEXER 1 AUGUST 1999 INDUSTRIAL TEMPERATURE RANGE The IDT logo is a registered trademark of Integrated Device Technology, Inc. ©1999 Integrated Device Technology, Inc. DSC-4722/1 FEATURES: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) •VCC = 3.3V ± 0.3V, Normal Range •VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4 µµµµµ W typ. static) • Rail-to-Rail output swing for increased noise margin • All inputs, outputs, and I/Os are 5V tolerant • Supports hot insertion • Available in QSOP, SOIC, SSOP, and TSSOP packages FUNCTIONAL BLOCK DIAGRAM DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems IDT74LVC138A DESCRIPTION: The LVC138A 3-line to 8-line decoder/demultiplexer is built using advanced dual metal CMOS technology. This device is designed for high- performance memory-decoding or data-routing applications requiring very short propagation delay times. In high performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decodersandtheenabletimeofthememoryareusuallylessthanthetypical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs selectoneofeightoutputlines.Twoactive-lowenableinputsandoneactive- high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external invert- ers and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC138A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH 5 VOLT TOLERANT I/O Y0 15 G1 Y1 14 Y2 13 Y3 12 A 1 2 3 B Select Inputs Data Outputs Enable Inputs G2A G2B 6 4 5 C Y4 11 Y5 10 Y6 9 Y7 7 |
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