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FIN24AC Scheda tecnica(PDF) 7 Page - Fairchild Semiconductor

Il numero della parte FIN24AC
Spiegazioni elettronici  USerDesTM 22-Bit Bi-Directional Serializer/Deserializer
Download  21 Pages
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FIN24AC Scheda tecnica(HTML) 7 Page - Fairchild Semiconductor

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Embedded Word Clock Operation
The FIN24AC sends and receives serial data source synchro-
nously with a bit clock. The bit clock has been modified to create
a word boundary at the end of each data word. The word
boundary has been implemented by skipping a low clock pulse.
This appears in the serial clock stream as 3 consecutive bit
times where signal CKSO remains HIGH. In order to implement
this sort of scheme two extra data bits are required. During the
word boundary phase the data will toggle either HIGH-then-
LOW or LOW-then-HIGH dependent upon the last bit of the
actual data word. Table 2 provides some examples showing the
actual data word and the data word with the word boundary bits
added. Note that a 24-bit word will be extended to 26-bits during
serial transmission. Bit 25 and Bit 26 are defined with-respect-to
Bit 24. Bit 25 will always be the inverse of Bit 24, and Bit 26 will
always be the same as Bit 24. This insures that a “0”
o “1”
and a “1”
o “0” transition will always occur during the embed-
ded word phase where CKSO is HIGH.
The serializer generates the word boundary data bits and the
boundary clock condition and embeds them into the serial data
stream. The deserializer looks for the end of the word boundary
condition to capture and transfer the data to the parallel port.
The deserializer only uses the embedded word boundary infor-
mation to find and capture the data. These boundary bits are
then stripped prior to the word being sent out of the parallel port.
TABLE 2. Word Boundary Data Bits
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold value
equal to ½ of VDDP. The input buffers are only operational when
the device is operating as a serializer. When the device is oper-
ating as a deserializer the inputs are gated off to conserve
power.
The LVCMOS 3-STATE output buffers are rated for a source/
sink current of 2 mAs at 1.8V. The outputs are active when the
DIRI signal is asserted LOW. When the DIRI signal is asserted
HIGH the bi-directional LVCMOS I/Os will be in a HIGH-Z state.
Under purely capacitive load conditions the output will swing
between GND and VDDP.
Unused LVCMOS input buffers must be tied off to either a valid
logic LOW or a valid logic HIGH level to prevent static current
draw due to a floating input. Unused LVCMOS output should be
left floating. Unused bi-directional pins should be connected to
GND through a high value resistor. If a FIN24AC device is con-
figured as an unidirectional serializer then unused data I/O can
be treated as unused inputs. If the FIN24AC is hardwired as a
deserializer then unused data I/O can be treated as unused out-
puts.
FIGURE 6. LVCMOS I/O
Differential I/O Circuitry
The FIN24AC employs FSC proprietary CTL I/O technology.
CTL is a low power, low EMI differential swing I/O technology.
The CTL output driver generates a constant output source and
sink current. The CTL input receiver senses the current differ-
ence and direction from the corresponding output buffer to
which it is connected. This differs from LVDS which uses a con-
stant current source output but a voltage sense receiver. Like
LVDS an input source termination resistor is required to properly
terminate the transmission line. The FIN24AC device incorpo-
rates an internal termination resistor on the CKSI receiver and a
gated internal termination resistor on the DS input receiver. The
gated termination resistor insures proper termination regardless
of direction of data flow. The relative greater sensitivity of the
current sense receiver of CTL allows it to work at much lower
current drive and correspondingly a much lower voltage.
During power-down mode the differential inputs will be disabled
and powered down and the differential outputs will be placed in
a HIGH-Z state. CTL inputs have an inherent failsafe capability
that supports floating inputs. When the CKSI input pair of the
serializer is unused it can reliably be left floating. Alternately
both of the inputs can be connected to ground. CTL inputs
should never be connected to VDD. When the CKSO output of
the deserializer is unused it should be allowed to float.
FIGURE 7. Bi-Directional Differential I/O Circuitry
24-Bit Data Words
24-Bit Data Word with Word Boundary
Hex
Binary
Hex
Binary
3FFFFFh
0011 1111 1111 1111 1111 1111b
1FFFFFFh 01 1111 1111 1111 1111 1111 1111b
155555h
0101 0101 0101 0101 01010 0101b
1155555h 01 0101 0101 0101 0101 0101 0101b
xxxxxxh
0xxx xxxx xxxx xxxx xxxx xxxxb
1xxxxxxh
01 0xxx xxxx xxxx xxxx xxxx xxxxb


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