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KM68B261A-8 Scheda tecnica(PDF) 6 Page - Samsung semiconductor |
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KM68B261A-8 Scheda tecnica(HTML) 6 Page - Samsung semiconductor |
6 / 7 page KM68B261A BiCMOS SRAM Rev 2.0 October-1994 6 Address /CS Data In /WE Data Out High-Z High-Z (10) (9) TIMING WAVE FORM OF WRITE CYCLE(2) (/OELowFixed) Data Valid tWC tWR(5) tDH tWHZ(6,7) tAW tCW(3) tWP(2) tAS(4) tOH tOW tDW NOTES (WRITE CYCLE) All write cycle timing is referenced from the last valid address to the first transition address. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low and /WE going low; A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. tCW is measured from the later of /CS going low to end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or /WE going high. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. Dout is the read data of the new address. When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. FUNCTIONAL DESCRIPTION /CS /WE /OE Mode I/O Pin Supply Current H L L L X H H L X* H L X Not Select Output Disable Read Write High-Z High-Z DOUT DIN ISB, ISB1 ICC ICC ICC *Note : X means Don't Care. |
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