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MC100EP223 Scheda tecnica(PDF) 4 Page - Motorola, Inc

Il numero della parte MC100EP223
Spiegazioni elettronici  Low-Voltage 1:22 Differential PECL/HSTL Clock Driver
Download  8 Pages
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Produttore elettronici  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC100EP223 Scheda tecnica(HTML) 4 Page - Motorola, Inc

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MC100EP223
MOTOROLA
TIMING SOLUTIONS
DL207 — Rev 0
4
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
MC100EP223
The MC100EP223 uses a thermally enhanced 64 lead
LQFP package. This package provides the low thermal
impedance that supports the power consumption of the
MC100EP223 high-speed bipolar integrated circuit and
eases the power management task for the system design. An
exposed pad at the bottom of the package establishes
thermal conductivity from the package to the printed circuit
board. In order to take advantage of the enhanced thermal
capabilitites of this package, it is recommended to solder the
exposed pad of the package to the printed circuit board. The
attachment process for exposed pad package is the same as
for any standard surface mount package. Vias are
recommended from the pad on the board down to an
appropriate plane in the board that is capable of distributing
the heat. In order to supply enough solder paste to fill those
vias and not starve the solder joints, it may be required to
stencil print solder paste onto the printed circuit pad. This pad
should match the dimensions of the exposed pad. The
dimensions of the exposed pad are shown on the package
outline in this specification. For thermal system analysis and
junction temperature calculation the thermal resistance
parameters of the package is provided:
Thermal Resistance
Convection
LFPM
RTHJAa
°C/W
RTHJAb
°C/W
RTHJCc
°C/W
RTHJBd
°C/W
Natural
57.1
24.9
100
50.0
21.3
200
46.9
20.0
15.8
9.7
400
43.4
18.7
800
38.6
16.9
a.
Junction to ambient, single layer test board, per JESD51-6
b.
Junction to ambient, four conductor layer test board (2S2P),
per JES51-6
c.
Junction to case, per MIL-SPEC 883E, method 1012.1
d.
Junction to board, four conductor layer test board (2S2P) per
JESD 51-8
It is recommended that users employ thermal modeling
analysis to assist in applying the general recommendations
to their particular application. The exposed pad of the
MC100EP223 package does not have an electrical low
impedance path to the substrate of the integrated circuit and
its terminals.


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