MC100ES6226

TIMING SOLUTIONS

7

MOTOROLA

Figure 4. MC100ES6226 AC test reference

Differential

Pulse Generator

Z = 50

W

RT = 50Ω

ZO = 50Ω

DUT

MC100ES6226

VTT

RT = 50Ω

ZO = 50Ω

VTT

APPLICATIONS INFORMATION

Maintaining Lowest Device Skew

The MC100ES6226 guarantees low output-to-output bank

skew of 35 ps and a part-to-part skew of max. TBD ps. To

ensure low skew clock signals in the application, both outputs

of any differential output pair need to be terminated

identically, even if only one output is used. When fewer than

all nine output pairs are used, identical termination of all

output pairs within the output bank is recommended. If an

entire output bank is not used, it is recommended to leave all

of these outputs open and unterminated. This will reduce the

device power consumption while maintaining minimum

output skew.

Power Supply Bypassing

The MC100ES6226 is a mixed analog/digital product. The

differential architecture of the MC100ES6226 supports low

noise signal operation at high frequencies. In order to

maintain its superior signal quality, all VCC pins should be

bypassed by high-frequency ceramic capacitors connected

to GND. If the spectral frequencies of the internally generated

switching noise on the supply pins cross the series resonant

point of an individual bypass capacitor, its overall impedance

begins to look inductive and thus increases with increasing

frequency. The parallel capacitor combination shown

ensures that a low impedance path to ground exists for

frequencies well above the noise bandwidth.

Figure 5. VCC Power Supply Bypass

VCC

MC100ES6226

VCC

33...100 nF

0.1 nF

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com