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74LVXC4245M Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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74LVXC4245M Scheda tecnica(HTML) 1 Page - STMicroelectronics |
1 / 11 page 1/11 July 2001 s HIGH SPEED: tPD = 6.5ns (MAX.) at VCCA = 5.0V, VCCB = 5.0V s LOW POWER DISSIPATION: ICCA = ICCB = 5µA(MAX.) at TA=25°C s LOW NOISE: VOLP =0.3V (TYP.) at VCCA=5.0V VCCB =3.3V s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCCA(OPR)=4.5V to 5.5V (1.2V Data Retention) VCCB(OPR)=2.7V to 5.5V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES C4245 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVXC4245 is a dual supply 8 bit configurable low voltage CMOS OCTAL BUS TRANSCEIVER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Designed for use as an interface between a 5V bus and a 3.3V to 5V bus in a mixed 5V/3.3V supply systems, it achieves high speed operation while maintaining the CMOS low power dissipation. This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated. The A-port interfaces with the 5V bus, the B-port with the 3.3V to 5V bus. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVXC4245 OCTAL DUAL SUPPLY BUS TRANSCEIVER PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R SOP 74LVXC4245M 74LVXC4245MTR TSSOP 74LVXC4245TTR TSSOP SOP |
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