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BD86852MUF-C Scheda tecnica(PDF) 6 Page - Rohm |
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BD86852MUF-C Scheda tecnica(HTML) 6 Page - Rohm |
6 / 46 page 6/43 TSZ02201-0A3A0AP00520-1-2 © 2020 ROHM Co., Ltd. All rights reserved. 03.Mar.2020 Rev.001 BD86852MUF-C www.rohm.com TSZ22111 • 15 • 001 Description of Blocks Internal Regulator (VREG) Block VREG is the linear regulator for PMIC use only (Do not use it for other purposes.). The VREG pin needs an appropriate external bypath capacitor. This is controlled by the EN1 internal signal. When the EN pin voltage is more than 2.6 V, the EN1 signal becomes high, and when it’s less than 0.8 V, the EN1 signal becomes low. VREG stops when the EN1 signal and the CTL1 internal signal are low. Reference Voltage (VREF1 and VREF2) Block Two independent reference voltages, one for the output voltage and the other for the voltage detections. Under Voltage Lock-Out Block for VCC (UVLO_VCC, UVLO_VREG and UVLO_VS) Input low-voltage detections for the VCC, VREG and VS2 pins. If any one of these input low-voltages are detected, the device goes into the UVLO state (See below for more details). UVLO_VCC and UVLO_VREG When UVLO is detected from these pins, all the outputs (VO1 to VO3 and EN_LDO) turn off immediately. And then, the PGOOD pin changes to low. Once the UVLO condition is removed, the device waits 200 µs (Typ) and starts VO1 rail power-up. UVLO_VS When UVLO is detected from VS2 pins, the secondary outputs (VO2, VO3 and EN_LDO) turn off immediately. And then, the PGOOD pin changes to low. Once the UVLO condition is removed, VO2, VO3 and EN_LDO turn on by the normal sequence. Thermal Shutdown Protection (TSD) Block To prevent IC from causing thermal destruction and thermal runaway, the TSD operates when chip temperature reaches 175 °C (Typ) or more. When TSD operates, all of the outputs (VO1 to VO3 and EN_LDO) turn off at the same time, and PGOOD changes low. IC resumes by sequence after chip temperature decreases to certain temperature. However, this thermal protection circuit is designed to protect IC itself from destruction. Do not exceed the chip temperature Tjmax = 150 °C. Oscillator (OSC) Block OSC generates clock for DC/DC1, 2, 3 and CONTROL block. The DC/DC1 operates in phase with the DC/DC3, and the DC/DC2 operates 180 degrees out of phase to reduce the input ripple current. Spread Spectrum Clock Generator (SSCG) Block OSC block built in spread spectrum clock generator (SSCG) function. Insert a capacitor of 3300 pF between SSCG pin and GND, it enables the spread-spectrum function. In this mode, the frequency is reduced by 5 % from the RT programmed center frequency and is modulated by ±3 % with 2.5 kHz modulation frequency. External LDO Controller (LDO_CNT) Block This IC outputs the control signal to External LDO from the EN_LDO pin. The power supply of the EN_LDO output buffer is VS2. When detection (LVD4 and OVD4) of external LDO output is necessary, short the external LDO output and FB_LDO. |
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