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M74DW66500B Scheda tecnica(PDF) 7 Page - STMicroelectronics |
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M74DW66500B Scheda tecnica(HTML) 7 Page - STMicroelectronics |
7 / 19 page 7/19 M74DW66500B tRHEL, whichever occurs last. See the M29DW640D datasheet for more details. Holding RPF at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the Flash memory is performing a Program or Erase operation. During Program or Erase op- erations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the Flash memory. When Byte/Word Organization Se- lect is Low, VIL, the Flash memory is in x8 mode, when it is High, VIH, the Flash memory is in x16 mode. PSRAM Chip Enable inputs (E1P, E2P). The Chip Enable inputs activate the PSRAM control logic, input buffers and decoders. E1P at VIH with E2P at VIH deselects the memory, reducing the power consumption to the standby level, whereas E2P at VIL deselects the memory and reduces the power consumption to the Power-down level, re- gardless of the level of E1P. E1P and E2P can also be used to control writing to the PSRAM memory array, while WP remains at VIL. It is not allowed to set EF1 or EF2 at VIL, E1P at VIL and E2P at VIH at the same time. PSRAM Upper Byte Enable (UBP). The Upper Byte Enable input enables the upper byte for PSRAM (DQ8-DQ15). UBP is active low. PSRAM Lower Byte Enable (LBP). The Lower Byte Enable input enables the lower byte for PSRAM (DQ0-DQ7). LBP is active low. VCCF Supply Voltage (2.7 to 3.3V). VCCF pro- vides the power supply for Flash memory opera- tions (Read, Program and Erase). The Command Interface is disabled when the VCCF Supply Voltage is less than the Lockout Volt- age, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCCF Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, ICC3. VCCP Supply Voltage (2.7 to 3.3V). VCCP pro- vides the power supply for the PSRAM. VSS Ground. VSS is the ground reference for all voltage measurements in the Flash and PSRAM chips. |
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